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mikx
145
deps/mysqllite/include/internal/atomic/x86-gcc.h
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deps/mysqllite/include/internal/atomic/x86-gcc.h
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#ifndef ATOMIC_X86_GCC_INCLUDED
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#define ATOMIC_X86_GCC_INCLUDED
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/* Copyright (C) 2006 MySQL AB
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
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/*
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XXX 64-bit atomic operations can be implemented using
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cmpxchg8b, if necessary. Though I've heard that not all 64-bit
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architectures support double-word (128-bit) cas.
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*/
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/*
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No special support of 8 and 16 bit operations are implemented here
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currently.
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*/
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#undef MY_ATOMIC_HAS_8_AND_16
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#ifdef __x86_64__
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# ifdef MY_ATOMIC_NO_XADD
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# define MY_ATOMIC_MODE "gcc-amd64" LOCK_prefix "-no-xadd"
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# else
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# define MY_ATOMIC_MODE "gcc-amd64" LOCK_prefix
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# endif
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#else
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# ifdef MY_ATOMIC_NO_XADD
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# define MY_ATOMIC_MODE "gcc-x86" LOCK_prefix "-no-xadd"
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# else
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# define MY_ATOMIC_MODE "gcc-x86" LOCK_prefix
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# endif
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#endif
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/* fix -ansi errors while maintaining readability */
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#ifndef asm
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#define asm __asm__
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#endif
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#ifndef MY_ATOMIC_NO_XADD
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#define make_atomic_add_body(S) make_atomic_add_body ## S
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#define make_atomic_cas_body(S) make_atomic_cas_body ## S
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#endif
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#define make_atomic_add_body32 \
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asm volatile (LOCK_prefix "; xadd %0, %1;" \
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: "+r" (v), "=m" (*a) \
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: "m" (*a) \
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: "memory")
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#define make_atomic_cas_body32 \
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__typeof__(*cmp) sav; \
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asm volatile (LOCK_prefix "; cmpxchg %3, %0; setz %2;" \
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: "=m" (*a), "=a" (sav), "=q" (ret) \
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: "r" (set), "m" (*a), "a" (*cmp) \
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: "memory"); \
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if (!ret) \
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*cmp= sav
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#ifdef __x86_64__
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#define make_atomic_add_body64 make_atomic_add_body32
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#define make_atomic_cas_body64 make_atomic_cas_body32
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#define make_atomic_fas_body(S) \
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asm volatile ("xchg %0, %1;" \
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: "+r" (v), "=m" (*a) \
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: "m" (*a) \
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: "memory")
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/*
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Actually 32/64-bit reads/writes are always atomic on x86_64,
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nonetheless issue memory barriers as appropriate.
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*/
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#define make_atomic_load_body(S) \
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/* Serialize prior load and store operations. */ \
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asm volatile ("mfence" ::: "memory"); \
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ret= *a; \
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/* Prevent compiler from reordering instructions. */ \
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asm volatile ("" ::: "memory")
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#define make_atomic_store_body(S) \
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asm volatile ("; xchg %0, %1;" \
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: "=m" (*a), "+r" (v) \
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: "m" (*a) \
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: "memory")
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#else
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/*
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Use default implementations of 64-bit operations since we solved
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the 64-bit problem on 32-bit platforms for CAS, no need to solve it
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once more for ADD, LOAD, STORE and FAS as well.
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Since we already added add32 support, we need to define add64
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here, but we haven't defined fas, load and store at all, so
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we can fallback on default implementations.
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*/
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#define make_atomic_add_body64 \
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int64 tmp=*a; \
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while (!my_atomic_cas64(a, &tmp, tmp+v)) ; \
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v=tmp;
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/*
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On some platforms (e.g. Mac OS X and Solaris) the ebx register
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is held as a pointer to the global offset table. Thus we're not
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allowed to use the b-register on those platforms when compiling
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PIC code, to avoid this we push ebx and pop ebx. The new value
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is copied directly from memory to avoid problems with a implicit
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manipulation of the stack pointer by the push.
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cmpxchg8b works on both 32-bit platforms and 64-bit platforms but
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the code here is only used on 32-bit platforms, on 64-bit
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platforms the much simpler make_atomic_cas_body32 will work
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fine.
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*/
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#define make_atomic_cas_body64 \
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asm volatile ("push %%ebx;" \
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"movl (%%ecx), %%ebx;" \
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"movl 4(%%ecx), %%ecx;" \
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LOCK_prefix "; cmpxchg8b %0;" \
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"setz %2; pop %%ebx" \
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: "=m" (*a), "+A" (*cmp), "=c" (ret) \
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: "c" (&set), "m" (*a) \
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: "memory", "esp")
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#endif
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/*
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The implementation of make_atomic_cas_body32 is adaptable to
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the OS word size, so on 64-bit platforms it will automatically
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adapt to 64-bits and so it will work also on 64-bit platforms
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*/
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#define make_atomic_cas_bodyptr make_atomic_cas_body32
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#ifdef MY_ATOMIC_MODE_DUMMY
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#define make_atomic_load_body(S) ret=*a
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#define make_atomic_store_body(S) *a=v
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#endif
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#endif /* ATOMIC_X86_GCC_INCLUDED */
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